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Section: Freelance programmers and web programmers resumes
Specialization: VHDL,Verilog, Perl, C, VC++, HPGL
Experience: 5Years 6 Months
Age: 28 years
Sex: Male
Foreign languages: English
Contact info:
First, Last name: Sheshikanth G
Phone: 91-80-66241419
E-mail: sheshikanth_2000@yahoo.com
Full description:
G. SHESHIKANTH, Mobile: +91-9845850384
L&T Infotech Limited, EmSyS Email: sheshikanth_2000@yahoo.com
Plot No. 25 - 31, EPIP 2nd Phase
KIADB Industrial Area, Whitefield,
Bangalore 560 066.
_______________________________________________________________________Experience summary
5+ years experience in front end designing of FPGA & CPLDs, System level designs for up to 1.2 million gates, high speed interfaces design & development.
• Currently working as FPGA Team Lead, Emsys, L&T, Bangalore
• FPGA & CPLD designs up to 1.2 million gate density.
• Patent filed for “Pre-mod-filter design for communication devices”.
• Digital Design & Soft IP Core development using VHDL
• Design & Development of Microprocessor / Micro controller based systems
• Software development using C, VC++ & assembly.
• High speed Board designs for up to 100 MHz.
• Worked on-site for 5 months at Suwon, South Korea for Samsung
Hardware Platforms • ALTERA, XILINX, Lattice, Actel Based FPGA & CPLD devices
• Atmel 89c51based Micro controller
• Microprocessor 8086,8085
• Motorola Power PC based designs
Software • VHDL
• VERILOG [Beginner Level]
• C, VC++, Assembly
Tools • Simulation Tools (Digital): ModelSim SE 6.2f, Active HDL-sim 4.2, Fusion/View Sim (Simulation), Waveformer Lite.
• Pspice – Analog: circuit simulation tools
• RTL Synthesis Tools: Sinplicity’s Synplify Pro8.1, Leonardo Spectrum Lev- 3, XILINX XST, Precision Synthesis
• Front End Tools: Mentor Graphics HDL Designer 2001.5a, XILINX ISE 8.2, ALTERA Quartus II 6.2, Actel Desktop, Libero –IDE (V5.1), FPGA Advantage, Active HDL 4.2 v, ISP Lever 6.1.
• Back end Tool: Designer Series-R2001&R2002 (Place and Route, Static Timing Analysis)
• Debugging Tools:
1. Logic Analyzers: Tektronix, Agilent Logical analyzers
2. Soft logic – Analyzers: Altera Signal Tap, Xilinx Chip Scope Pro, Identify Instrumentor, debugger & In-Circuit Emulator.
• Board Design Tools:
Cadence ORCAD 9.2, Innoveda (VIEW Draw)
Protocols • I2C protocol for serial RTC
• Serial Communication Protocols (USB, I2C), RS232 & RS485
From June –2006 to Till Date
Project Name Design & Development of Multi-function data acquisition product, which is aimed primarily at the utility distribution market and offers Fault Recording, Fault Location, Power Quality, SER functions, PMU , POW & RTU.
Details Type: Fault Recording FPGA design
Domain: Utility distribution market
System Frequency: 100 MHz
Description: FPGA design comprises of the following functions.
Sampling & data acquisition, Data alignment, decimation function, Triggers Handling, Scheduler, SDRAM controller, Time synchronization module & synchronization algorithms, Time of Day Functions, IRIGB Encoder, DFR record formation for different trigger types, Events Log formation, Power PC I/F in memory mapped mode, PIC I/F using SPI Master, FL FPGA in SPI slave mode, Register control Interface module.
AFE I/F [100MHz]:
9 analog channels and 16 digital channels – sampling Engine, Offset calibration, Gain calibration, floating point multiplication unit as per IEEE754 32-Bit floating format.
DSP I/F [12.5MHz] – SPI –Master module design [4-wire Full duplex communication], Data aligner, Packet encoder, Packet decoder.
CPU I/F [50MHz]:
Power PC Interface in memory-mapped mode, register control interface with read only, write only and read/write access, interrupt handling module. Protocol handler functions.
PIC I/F: SPI Master [2MHz] TOD maintenance, PIC Command controller,
SDRAM Controller I/F [50 MHz]: SDRAM Scheduler, SDRAM Controller
Device: Xilinx Spartan 3E Device XC3S1200E-4FG320I
Debugging: Verification of FPGA using chip scope pro & Tektronix logic analyzer, Code warrior tools for CPU I/F debugging, Code composer studio for DSP I/F Test
Team Size 7
Role & Contribution • Role: FPGA Team Lead
• Team Management activities, Issue resolution & status tracking, client interaction.
• Requirement elicitation
• Interfaces design, Micro architecture for the FR_FPGA, design documents preparation, integrated test plans, system test plans & test procedures document.
• RTL Coding, test bench & simulation.
• Board level debugging.
• Support at the time of system integration testing.
From April –2006 to May 2006
Project Name Wide Angle Bar Code Reader Daughter Card design
Details Type: FPGA design & Board Design
Domain: Used in US Postal department for envelope scanning
System Frequency: 48 MHz
WABCR Daughter Card Design: This daughter card is used to create the packet compatibility between the existing 16 Bit ACCU-LINK image encoder with already existing 8-Bit Camera module. It Does packet encoding and synchronization.
Device: APEX10K Device
Debugging: Used signal tap logic analyzer & Tektronix logic analyzer.
Team Size 2
Role & Contribution • Role: Project Lead
• Requirement elicitation, offshore technical support at the time of system integration
• Team Management activities, Issue resolution & status tracking
• Interfaces design, micro architecture for the FPGA, design document preparation, test plans & test procedures document.
• RTL Coding, test bench & simulation.
• Board level debugging.
• Support at the time of system integration testing.
From Nov –2005 to April 2006
Project Name Range Finder Camera Design, Image Processing Implementation in FPGA
Details Type: CPLD & FPGA Design & Development
Domain: Used in Conveyer Belt Application for Parcel Scanning
System Frequency: 66 MHz
Range Finder: The range finder camera design is done incorporating a CPLD for generating CCD Sensor [Toshiba-TCD1209D] & AFE [AD9804] timings. This is for a line camera application with the necessary analog front-end interface for capturing the pixel data configurable for different line rates. And further sent on WEIM Interface of iMX31processor.
Image Processing in FPGA:
The Image Processing Blocks implemented in FPGA consists of the following functions. This includes complex algorithms used for image processing and data encoding.
 Test pattern generation/capture
 Gain/Offset adjustment
 Image mirror
 Digital zoom
 Fixed digital gain
 Histogram Equalization
 Binary generation (& Black-Fill)
 Data masking
 Data encoding
Device: StratixGX
Debugging: Verification of Ranger Camera & Image processing Block using signal tap logic analyzer, agilent logic analyzer.
Team Size 3
Role & Contribution • Role: Team Member
• Requirement elicitation, Board design for range finder camera, BOM preparation, assisting the CAD team during placement & routing & BBT.
• Interfaces design, design document preparation, test plans & test procedures document.
• RTL Coding, test bench & simulation.
• Static Timing Analysis, Board level debugging.
• Support at the time of system integration testing.
From June –2005 to Nov -2005
Project Name High Speed Interfaces Design for 4G Trial System
4G Modem Application for SAMSUNG
[On-Site for 5 Months in South Korea]
Details Type: Design & Development
Domain: 4G-Modem Application
System Frequency: 125 MHz
Interfaces Developed: Linkport interface between Stratix GX FPGA and TigerSHARC DSP. Designed, developed and tested for 1Gbps throughput. Linkport provides DSP-QUAD-UART Interface, DSP –Ethernet (1Gbps) Interface, DSP-DPA (Dynamic Phase Aligner) Interface, to transfer the data acquired by the antenna-capture-module to DSP. Other interfaces include 22-channel DPA (125MHz x 8-bit data/clock) interface, 18-Channel GXB (Giga-Bit Transciever Buffers) Interface. High speed NtRAM Interface, Quad-Uart interface, Register control interface & Ethernet interface using NIOS core.
Device: StratixGXEP1SGX40GF1020C5
Stratix II EP2S180F1508C4
Debugging: Verification of Channel card using signal tap logic analyzer, agilent logic analyzer.
Team Size 3
Role & Contribution • Role: Team Member
• Requirement elicitation
• Interfaces design, design document preparation, test plans & test procedures document.
• RTL Coding, test bench & simulation.
• Static Timing Analysis, Board level debugging.
• Top-level image preparation.
• Support at the time of system integration testing.
• Preparation of Loop back test images.
From Jan –2005 to May -2005
Project Name DRC POWER SUPPLY FPGA Design
Details Description:
Type: Re-Engineering
Domain: Mass spectrometry
The scope of work is to convert the schematics into VHDL Code. Single
FPGA Solution is proposed, taking Obsolescence Into consideration.
XC2S15-6TQ144C FPGA is used for the Implementation. The DRC
POWER SUPPLY FPGA has a Synchronous serial link Interfaced to
System controller and a DDS Interface to external Analog Circuitry.
Functionality:
The DRC board is interfaced with system controller using SSL (Synchronous Serial Link) signals. These SSL signals provide a communication link between the System Controller board and the DRC POWER SUPPLY board. The system controller through SSL sends address, data and other interface signals for the DDS chip, Resolution DAC and Rod Offset DACs and POWER SUPPLY ENABLE inputs to the RF Section. It provides the necessary addressing, data, and control signals for the DACs.
DDS Interface: The DDS Interface module of DRC-FPGA provides the word clock, Frequency update signals, DDS Reset signal and Frequency tuning words according to the timing requirements of AD9851 DDS chip. The loading and Timing of these tuning words are governed by Settling and Increment signals from the SCAN Control & Timing signals from System Controller.
Team Size 2
Role & Contribution • Requirement analysis & Design
• Block level integration, timing simulation, selecting devices and board designing.
• RTL Coding of DRC POWER SUPPLY FPGA modules using VHDL.
• Static Timing Analysis
• Test Cases & Test Bench to check the functionality of DRC POWER SUPPLY FPGA.
From Nov –2004 to Jan – 2005
Project Name QPS-ELAN
Details Description:
Type: Re-Engineering
Domain: Mass spectrometry
The scope of work is to convert the schematics into VHDL Code and implement the QPS-ELAN design in a XILINX FPGA (XC2S15-6TQ144C). Single FPGA Solution is proposed, taking Obsolescence Into Consideration. The QPS-ELAN FPGA has a synchronous serial link interface to system controller and a MASSDAC interface to external analog circuitry.
Functionality:
The SSL (Synchronous Serial Link) signals provide a communication link between the System Controller board and the QPS ELAN board. The SSL sends address and data signals for the Mass, Resolution and Rod Offset DACs.
Mass DAC module provides the necessary addressing, data, and control signals for the MASS DAC’s. The 16-bit Mass DAC’s have a 16 bit data bus which is loaded in one operation
The SSL sends 16 bits of data, and the FPGA logic takes care of the loading and timing. The FPGA also incorporates a pre-load register and counter for the Mass DAC. FPGA selects the appropriate mass DAC to load or increment, and the Mass DAC’s are configured in transparent mode, i.e. the DAC responds instantly to changes on the data bus.
Team Size 2
Role & Contribution • Requirement analysis & Design
• Block level integration, timing simulation, selecting devices and board designing.
• RTL Coding of QPS-ELAN modules using VHDL
• STA (Static Timing Analysis)
• Test plans & Test bench to test the functionality of QPS-ELAN.
From Oct –2004 to Nov 2004
Project Name CPLD Design for Reset module
Details This Project implements the reset module for DSP & analog interfaces. The CPLD performs Power on Initialization of the ADC, Reads Status from the ADC after RESET cycle and generates the signals necessary for Normal Operation of ADC & Other analog interfaces. Xilinx Cool Runner series CPLD is used for this project. CPLD provides the following interfaces on the board: 16-Bit ADC (TLC4541) interface to the SPI port of DSP (TMS320VC5502). Chip select Logic is Implemented for QUAD_UART (16C554), FLASH (29LV160D), NVRAM/FRAM (FM18L08) and (16 X 1, 2 X 1) MUX Interface.
Team Size 1
Role & Contribution • Requirement analysis & Design
• Block level integration, timing simulation, selecting devices and board designing.
• RTL Coding in VHDL
• Test plans & Test Bench to test the functionality of reset module.
• Debugging on Board
From Jul –2004 to Oct 2004
Project Name QPS-EXCITER
Details Description:
Type: Re-Engineering
Domain: Mass spectrometry
This Project is meant for mass spectrometry based application. The
QPS- Exciter FPGA has a synchronous serial link interface to system
Controller and a MASSDAC interface to external analog circuitry.
The scope of work is to implement the QPS-Exciter design in a
XILINX FPGA. Except for some design changes the Functionality of
QPS- ELAN & QPS-Exciter is one and the same. FPGA Used is
XC2S30- 6TQ144C
Team Size 2
Role & Contribution • Requirement analysis & Design
• Block level integration, timing simulation, selecting devices and board designing.
• RTL Coding of QPS- Exciter modules using VHDL
• Test Plans & Test Bench to test the functionality of QPS-Exciter.
From June –2004 to Jul 2004
Project Name PS/2 Keyboard controller in VHDL
Details The scope of this project is to implement a PS/2 Compatible soft core for PS/2 devices like Keyboard & mouse. It provides a bi-directional, synchronous serial interface between a host and a ps/2 device. It has hardware parity (Odd) check on all data received from PS/2 Device and it is wish bone compliant.
Team Size 1
Role & Contribution • Requirement analysis
• Feasibility study and Design
• Static Timing Analysis
• RTL Coding in VHDL
• Test bench & Functional Verification & System testing.
Project Name I2C slave Implementation for uc interface
Details Description:
The I2C Controller design consists of asynchronous micro controller (µC) interface and provides I2C Slave capability.
The I2C protocol implementation defines a data transfer format for both 7-bit and 10-bit addressing. The implementation of the I2C controller in the Xilinx FPGA for COMIO supports the seven-bit address format. The Micro Controller interface for the I2C controller design supports an asynchronous byte-wide bus protocol. This protocol is the method in which the micro controller reads and writes the registers in the design. Micro controller is operated on 22.1184MHz clock.
Team Size 1
Role & Contribution • Requirement analysis & Design
• Architectural level designing, block level integration, timing simulation, selecting devices and board designing.
• RTL Coding in VHDL
• Test Plan & Test bench for functional verification.
Project Name “Intelligent PCM Encoder for Military Air-craft”
Details Description: The scope of the project is to develop a Pulse Code Modulation Encoder, to transmit the time critical sensors data from cockpit to the ground station using an RF radio link. The PCM encoder card is of PMC form factor and is designed to operate at 32.768 MHz clock. This card is developed in compliance with VITA-20-2002 Standard. The board provides the standard interconnects like PCI Interface, RS-422 Interface, I2C Interface etc
Functionality: The PCM Encoder packetizes the sensors data (That is of Critical Importance), which is stored in the shared memory of DACENT (Data Center), Through PCI bus. The PCI Interface is through PLX-PCI-9054 (PCI-PCI) bridge. The packetising is according to the standard IRIG-B (& IRIG 106 for Time stamp) frame format. The local bus of the PCI Bridge is interfaced to FPGA, DPRAM, RS-422 module and Out put module. FPGA in the PCME plays a major role in implementing the total functionality of the card. All programmable features like Frame length, Major frame counter, Minor frames/ Major Frame, Word length, Frame sync, SFID (SUB-Frame ID), IRIG Time, RS-422 Option, output bit rate selection, Pre-Modulation Filter (With variable cut-off Frequencies) and output level control are implemented in FPGA. Actel Pro-Asic device with 300K-gate count is used in this design.
Team Size 3
Role & Contribution • Architectural level designing, block level integration, timing simulation, selecting devices and board designing.
• Signal Integrity analysis and Power Analysis at component level & RTL Coding of PCME modules using VHDL
• Designing of BIST (Built In Self Test) Cases to test the functionality of PCME.
• Design and development of Bessel 6th order low pass filter.
• Development of In-House Filter Response Analyzer using C-Graphics & Documentation related activities (As per MIL-STD-2167A Standard)
Project Name “BIT (Built In Test) software for SCT (Structural Coupling Test) Facility”
Details Description: For any military aircraft, before takeoff, many RFT’s (Request For Tests) are to be performed to check the functionality of entire system and various subsystems on the aircraft. Performing these tests is a tedious and time-consuming job. Several GPIB, VXI and other special interface instruments are connected to various subsystems on the aircraft to carry out the functional verification. As a result, need arises for these instruments to work reliably.
At any point of time if any of the instruments fails to work, total TEST has to be aborted and is to be re performed. To avoid this difficulty “Built In Test Software for SCT” facility is developed to configure, Check for presence of all instruments and perform instrument specific built in tests for GPIB, VXI and other special interface related equipments.
Functionality:
The Built In Test software is a GUI based application developed in VC++. It is used
1) To configure the instruments categorically (GPIB, VXI, Special Interfaces) by setting the logical address.
2) To scan for the presence of all instruments that are configured.
3) To Perform instrument specific Built in Test and
4) To generate error reports (Detailed, Condensed)
Team Size 2
Role & Contribution • Coding for GPIB instruments (FRA (Frequency Response Analyzer), Thermal Array-corder and MCA (Multi Channel Analyzer)), Special interface instruments (BOB (Break Out Box)) and Relay matrix of VXI.
• System testing, Integration & Project Co-ordination.
• Generating test cases for the BIT software.
• Documentation of SRS (Software Requirements Specifications), SDP (Software development Plan), DDD (Detailed Design Document) etc., (As per MIL-STD-2167A Standard)
Project Name “Rotor Telemetry PCM Acquisition & Analysis Software”
Details Description:
The Rotor Telemetry PCM Acquisition & Analysis Software is a GUI based application developed in VC++ using MFC application wizard. The software will interact with ISA bus based decommutator hardware that is plugged on to the Portable workstation.
The drivers for this decommutator are developed in WIN NT. This application displays the configured parameters data in Textual and graphical format. This software is meant to analyze the time critical parameters data both online & Offline.
Functionality:
User has to configure the frame format and the Decommutator hardware settings from the options provided. The Frame format configuration data is stored in a Master file, where user creates selected pages from the page configuration screen. The user can see the parameter values varying while the application is selected for online mode. For off line analysis the user selected parameters are processed for selected time duration and displayed with all the samples. The user is provided with sample-to-sample spacing option, Number of samples to plot etc.
Team Size 2
Role & Contribution • Coding, testing with simulator, logged data analysis.
• System testing, Integration & Project Co-ordination.
• Generating test cases for the Rotor PCM Telemetry software.
• Documentation related activities.
• Client interaction for User Screens.
Project Name “Simulation of 802.3 MAC (Ethernet Protocol) Transmitter Using VHDL”
Details Description :
In This Project, using IEEE 802.3 MAC protocol (Ethernet Protocol) Transmitter part is implemented using VHDL. This includes RTL coding, Functional Verification, Test bench for different test cases. This implementation is at MAC sub-layer.
Team Size 2
Role & Contribution • Architectural level designing, block level integration, timing simulation.
• RTL Coding of 802.3 MAC transmitter modules using VHDL
• Test Cases to test the functionality of 802.3 MAC transmitter.
Project Name “Implementation of Plotter drivers to plot the Real-time Telemetry data continuously on a HP plotter”
Details Description:
This project is to enable real time data plotting on an HP750c design jet plotter. The plotter drivers developed will convert the Real-time data that is acquired by the Add-On hardware with in the system, to HPGL commands. The time slack for these drivers is very minimal as the data is converted into respective HPGL command online.
Functionality:
The plotter drivers will convert the real time continuous data into Respective HPGL commands. The plotter application will plot the Grid and axes values before actually plotting the data. This conserves the printing and spooling time.
Team Size 2
Role & Contribution • Coding, Analyzing the HPGL commands.
• System testing, Integration & Project Co-ordination.
• Generating test cases for the Plotter Application.
• Documentation related activities.
Gender Male
Date of Pass Out May 2002
Passport Details A9853691
Current Visa Status L1-Blanket Visa to US
Qualification B.Tech in Electronics & Communications
Current CTC 6.724 Lac Per Annum
Achievements Patent filed for “Pre-mod-filter design for communication devices”.
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